This invention relates to a semiconductor integrated circuit device, and, more particularly, to the improvement of the clock driver section of a large scale integrated circuit (abbreviated as LSI).
With reference to the LSI, a large number of gate circuits and flip-flop circuits are operated in synchronization with a clock signal. Consequently, a clock signal line which extends all over an LSI chip is connected to numerous load circuits. The total capacity of all the load circuits amounts to as much as scores of hundreds of [pF] units. A clock driver for actuating a clock signal line connected to such a large capacity load must have a large drivability.
When a clock driver having a large drivability is set in the LSI, the following difficulties are encountered.
(1) A large current change appears in the clock driver section leading to the occurrence of local switching noises, potential changes in a power line, and also a prominent flow of substrate current. As a result, drawbacks arise in that the circuit malfunctions, and the CMOS-LSI becomes subject to breakage resulting from latch-up phenomenon.
(2) It has been proposed to lay a broad power line and ground line near the clock driver as a means of resolving the above-mentioned problems. However, this process presents difficulties in the drawing of a pattern layout on the LSI. Particularly with automatic placement and routing by a computer, the wiring width is generally restricted, making it difficult to locally broaden a power line.
(3) A clock pulse is supplied from a single clock driver to a plurality of load circuits distributed over the LSI chip substrate. Consequently, signal lines around the clock driver are extremely congested, another factor presenting difficulties in defining a pattern layout.
For the resolution of the aforementioned drawbacks, it has hitherto been attempted to distribute a plurality of clock drivers generating the same clock signal over a plurality of points on the LSI chip substrate. This process can, indeed, resolve the problems described in the foregoing items (1) to (3). The mere distribution of the clock drivers, however, is itself accompanied by a drawback related to the clock skew.
Description may now be made of this problem with reference to the accompanying FIG. 9. In the example of FIG. 9, one output signal from the clock generator 21 is supplied to two divided clock drivers 22.sub.1, 22.sub.2. These clock drivers 22.sub.1, 22.sub.2 supply clock signals CL.sub.1, CL.sub.2, respectively, to their corresponding clock signal lines 23.sub.1, 23.sub.1. Though the two clock signals CL.sub.1, CL.sub.2 are issued at the same time, the clock drivers 22.sub.1, 22.sub.2 indicate different delay properties, depending on the load condition.
FIG. 10 indicates the waveforms of the clock signals CL.sub.1, CL.sub.2. The characters t.sub.p1, t.sub.p2 represent the length of time required for the clock signals CL.sub.1, CL.sub.2, respectively, to have their logic data converted from "1" to "0". A difference .DELTA.t.sub.p between the two lengths of time denote a clock skew. This clock skew adversely affects the operation of the subject semiconductor integrated circuit device.
In this connection, reference is made to FIG. 11, showing the operation of a shift register comprising a plurality of successively connected J-K flip-flop circuits. The flip-flop circuit 24.sub.1 of the nth order is operated by the clock signal CL.sub.1 of FIG. 10. The flip-flop circuit 24.sub.2 of the n+1th order, and the flip-flop circuit 24.sub.3 of the n+2th order are operated alike by the clock signal CL.sub.2 of FIG. 10. If the length of time required for the negative edge trigger type flip-flop circuit of FIG. 10 to have its logic data changed from "1" to "0" happens to be shorter than the aforesaid clock skew .DELTA.t.sub.p, then the flip-flop circuit 24.sub.1 of the nth order has its condition changed before the flip-flop circuit 24.sub.2 of the n+1th order is triggered. As a result, incorrect data is transmitted to the flip-flop circuit 24.sub.2 of the n+1th order. If, therefore, a clock driver is simply divided into a plurality of components, the semiconductor integrated circuit device will malfunction, causing, for example, incorrect data to be transmitted due to a different load condition of the clock driver.